Signal multiplexer

ABSTRACT

A signal multiplexer according to the present embodiment has a configuration sufficiently capable of accelerating a data rate. The signal multiplexer includes M number of front units and a rear unit. An m-th front unit A m  outputs an output signal corresponding to an m-th input signal I m  when both the control signal C m  and the control signal C n  are significant levels, and outputs an output signal having a fixed level when at least either one of the control signal C m  or the control signal C n  is an non-significant level. A rear unit B receives signals from the front units, and outputs a signal having a different signal level in a case in which all the output signals from the front units are the same level or in the other case.

TECHNICAL FIELD

The present invention relates to a signal multiplexer.

BACKGROUND

Jihwan Kimetal., “A 16-to-40 Gb/s Quarter-Rate NRZ/PAM4 Dual-ModelTransmitter in 14 nm CMOS”, 2015 IEEE International Solid-State CircuitsConference (ISSCC), (US), February, 2015 (hereinafter, referred to asNon-Patent Literature 1) discloses a signal multiplexer whichmultiplexes four input signals and outputs one output signal(multiplexed signal). The signal multiplexer includes four buffersections connected in parallel. Each buffer section includes a flip-flopand two transfer gates which are sequentially connected in series. Eachtransfer gate is adjusted so as to be turned ON at a predeterminedtiming. Thus, input signals input to the buffer sections aresequentially output from the signal multiplexer as one output signal.

According to the signal multiplexer disclosed in Non-Patent Literature1, it is possible to extend the allowable range of the delay time of aflip-flop and accelerate the data rate compared with the case in whichtwo input signals are multiplexed and one output signal is output.

SUMMARY

The inventors have studied a conventional signal multiplexer and foundthe following problem. That is, in the signal multiplexer disclosed inNon-Patent Literature 1, the load capacity value becomes high becauseone connecting point with which all the output ends of the four buffersections are connected is formed. For this reason, the waveform of anoutput signal becomes dull, and the frequency band is restricted.Consequently, acceleration of the data rate has been limited in aconventional signal multiplexer.

The present invention has been made to solve such a problem as describedabove, and is to provide a signal multiplexer having a configurationsufficiently capable of accelerating the data rate compared with theconventional signal multiplexer.

A signal multiplexer according to the present embodiment outputs asignal (an input signal, a logically inverted signal thereof, and thelike) corresponding to an input signal I_(m) of M number of inputsignals I₁ to I_(M) sequentially designated based on a combination ofsignal levels of an m-th control signal C_(m) and an n-th control signalC_(n) which are selected from M number of control signals C₁ to C_(M),where M is an integer defined by 2^(i), i is an integer of 2 or greater,m is an integer of 1 to M, and n is an integer of 1 when m=M, and of m+1when m<M, while the combination of the signal levels are beingmaintained. Specifically, the signal multiplexer includes M number offront units A₁ to A_(M) corresponding to the M number of input signalsI₁ to I_(M), and a rear unit electrically connected with output ends ofthe front units A₁ to A_(M). An m-th front unit A_(m) of the M number offront units A₁ to A_(M) outputs an output signal corresponding to theinput signal I_(m) input to the front unit A_(m) when both signal levelsof the control signal C_(m) and the control signal C_(n) aresignificant. On the other hand, the front unit A_(m) outputs an outputsignal having a fixed signal level when at least either signal level ofthe control signal C_(m) or the control signal C_(n) is non-significant.The rear unit receives the output signals from the front units A₁ toA_(M), and outputs, as the signal corresponding to the input signalI_(m), a signal having a different signal level in a case in which allthe output signals from the front units A₁ to A_(M) are the same signallevel or in the other case.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a signal multiplexer 1according to the present embodiment;

FIG. 2 is a table showing the relation of signal levels of controlsignals C₁ to C_(M), output signals of front units A₁ to A_(M), and anoutput signal of a rear unit B in the signal multiplexer 1 according tothe present embodiment;

FIG. 3 is a timing chart of control signals C₁ to C_(M), input signalsI₁ to I_(M), and an output signal of the rear unit B;

FIG. 4 is a diagram showing a configuration example of a generation unit2 when M=8;

FIG. 5 is a timing chart of a clock CLK1, a logically inverted signal ofthe clock CLK1, a clock CLK2, a clock CLK3, and control signals C₁ to C₈when M=8;

FIG. 6 is a diagram showing a first configuration example of a frontunit A_(m);

FIG. 7 is a diagram showing a second configuration example of the frontunit A_(m);

FIG. 8 is a diagram showing a first configuration example of the rearunit B;

FIG. 9 is a diagram showing a second configuration example of the rearunit B;

FIG. 10 is a diagram showing a third configuration example of the rearunit B;

FIG. 11 is a diagram showing a third configuration example of the frontunit A_(m);

FIG. 12 is a diagram showing a fourth configuration example of the frontunit A_(m);

FIG. 13 is a diagram showing a fourth configuration example of the rearunit B;

FIG. 14 is a diagram showing a fifth configuration example of the rearunit B; and

FIG. 15 is a diagram showing a sixth configuration example of the rearunit B.

DETAILED DESCRIPTION Description of Embodiments of the Present Invention

First, embodiments of the present invention are individually describedin order.

(1) A signal multiplexer according to the present embodiment outputs asignal (an input signal, a logically inverted signal thereof, and thelike) corresponding to an input signal I_(m) of M number of inputsignals I₁ to I_(M) sequentially designated based on a combination ofsignal levels of an m-th control signal C_(m) and an n-th control signalC_(n) which are selected from M number of control signals C₁ to C_(M),where M is an integer defined by 2^(i), i is an integer of 2 or greater,m is an integer of 1 to M, and n is an integer of 1 when m=M, and of m+1when m<M, while the combination of the signal levels are beingmaintained. As a first aspect, the signal multiplexer includes M numberof front units A₁ to A_(M) corresponding to the M number of inputsignals I₁ to I_(M), and a rear unit electrically connected with outputends of the front units A₁ to A_(M). An m-th front unit A_(m) of the Mnumber of front units A₁ to A_(M) outputs an output signal correspondingto the input signal I_(m) input to the front unit A_(m) when both signallevels of the control signal C_(m) and the control signal C_(n) aresignificant. On the other hand, the front unit A_(m) outputs an outputsignal having a fixed signal level when at least either signal level ofthe control signal C_(m) or the control signal C_(n) is non-significant(insignificant). The rear unit receives the output signals from thefront units A₁ to A_(M), and outputs, as the signal corresponding to theinput signal I_(m), a signal having a different signal level in a casein which all the output signals from the front units A₁ to A_(M) are thesame signal level or in the other case.

(2) As a second aspect applicable to the first aspect, the front unitA_(m) may include a first transistor group including three PMOStransistors and a second transistor group including two NMOStransistors. In the first transistor group, a first PMOS transistorT_(P1) includes a source electrically connected with an upper-limitreference end set to upper-limit reference potential, a gate, and adrain. A second PMOS transistor T_(P2) includes a source electricallyconnected with the drain of the first PMOS transistor, a gate, and adrain. A third PMOS transistor T_(P3) includes a source electricallyconnected with the drain of the second PMOS transistor, a gate, and adrain. Any one of the input signal I_(m), the control signal C_(m), andthe control signal C_(n) is exclusively input to the gate of each of thefirst to third PMOS transistors T_(P1) to T_(P3). On the other hand, inthe second transistor group, a first NMOS transistor T_(N1) includes adrain electrically connected with the drain of the third PMOS transistorT_(P3), a gate, and a source electrically connected with a firstlower-limit reference end set to first lower-limit reference potentiallower than the upper-limit reference potential. A second NMOS transistorT_(N2) includes a drain electrically connected with the drain of thethird PMOS transistor T_(P3), a gate, and a source electricallyconnected with a second lower-limit reference end set to secondlower-limit reference potential lower than the upper-limit referencepotential. Either one of the control signal C_(m) or the control signalC_(n) is exclusively input to the gate of each of the first and secondNMOS transistors T_(N1) and T_(N2). Furthermore, the connecting pointsbetween the drain of the third PMOS transistor T_(P3) and the drains ofthe first and second NMOS transistors T_(N1) and T_(N2) are electricallyconnected with the rear unit.

(3) As a third aspect applicable to the first aspect, the front unitA_(m) may include a first gate circuit and a second gate circuit. Thefirst gate circuit outputs a signal indicating a logical NAND betweentwo of the input signal I_(m), the control signal C_(m), and the controlsignal C_(n). The second gate circuit outputs a signal indicating alogical NOR between the output signal of the first gate circuit and theother one of the input signal I_(m), the control signal C_(m), and thecontrol signal C_(n).

(4) The rear unit according to a fourth aspect applicable to the secondor third aspect may have a configuration capable of receiving outputsignals from the front units A₁ to A₄ of the front units A₁ to A_(M) (aconfiguration when M=4). In this case, the rear unit having theconfiguration when M=4 may include two third gate circuits G₃₁ and G₃₂,and a fourth gate circuit G₄. The third gate circuits G₃₁ and G₃₂ eachexclusively receive two signals of the output signals from the frontunits A₁ to A₄. Then, the third gate circuits G₃₁ and G₃₂ each output asignal indicating a logical NOR between the received signals. On theother hand, the fourth gate circuit G₄ receives the signals output fromthe third gate circuits G₃₁ and G₃₂, and outputs a signal indicating alogical NAND between the received signals.

(5) The rear unit according to a fifth aspect applicable to the secondor third aspect may have a configuration capable of receiving outputsignals from the front units A₁ to A₄ of the front units A₁ to A_(M) (aconfiguration when M=4). In this case, the rear unit having theconfiguration when M=4 may include two third gate circuits G₃₁ and G₃₂,and a fourth gate circuit G₄. The third gate circuits G₃₁ and G₃₂ eachexclusively receive two signals of the output signals from the frontunits A₁ to A₄. Then, the third gate circuits G₃₁ and G₃₂ each output asignal indicating a logical NOR between the received signals. The fourthgate circuit G₄ receives the signals output from the third gate circuitsG₃₁ and G₃₂, and outputs a signal indicating a logical AND between thereceived signals.

(6) The rear unit according to a sixth aspect applicable to the firstaspect may have a configuration capable of receiving output signals fromthe front units A₁ to A₈ of the front units A₁ to A_(M) (a configurationwhen M=8). In this case, the rear unit in the configuration when M=8 mayinclude four third gate circuits G₃₁ to G₃₄, two fourth gate circuitsG₄₁ and G₄₂, and a fifth gate circuit G₅. The third gate circuits G₃₁ toG₃₄ each exclusively receive two signals of the output signals from thefront units A₁ to A₈. Then, the third gate circuits G₃₁ to G₃₄ eachoutput a signal indicating a logical NOR between the received signals.The fourth gate circuit G₄₁ and G₄₂ each exclusively receive two signalsof the signals output from third gate circuits G₃₁ to G₃₄. Then, thefourth gate circuits G₄₁ and G₄₂ each output a signal indicating alogical NAND between the received signals. The fifth gate circuit G₅receives the signals output from the fourth gate circuits G₄₁ and G₄₂,and outputs a signal indicating a logical NOR between the receivedsignals.

(7) As a seventh aspect applicable to the first aspect, the front unitA_(m) may include a first transistor group including two PMOStransistors and a second transistor group including three NMOStransistors. In the first transistor group, a first PMOS transistorT_(P1) includes a source electrically connected with a first upper-limitreference end set to first upper-limit reference potential, a gate, anda drain. A second PMOS transistor T_(P2) includes a source electricallyconnected with a second upper-limit reference end set to secondupper-limit reference potential, a gate, and a drain. Either one of thecontrol signal C_(m) or the control signal C_(B) is exclusively input tothe gate of each of the first and second PMOS transistors T_(P1) andT_(P2). On the other hand, in the second transistor group, a first NMOStransistor T_(N1) includes a drain electrically connected with thedrains of the first and second PMOS transistors T_(P1) and T_(P2), agate, and a source. A second NMOS transistor T_(N2) includes a drainelectrically connected with the source of the first NMOS transistorT_(N1), a gate, and a source. A third NMOS transistor T_(N3) includes adrain electrically connected with the source of the second NMOStransistor T_(N2), a gate, and a source connected with a lower-limitreference end set to lower-limit reference potential than the first andsecond upper-limit reference potential. Any one of the input signalI_(m), the control signal C_(m), and the control signal C_(n) isexclusively input to the gate of each of the first to third NMOStransistors T_(N1) to T_(N3). Furthermore, the connecting points betweenthe drains of the first and the second PMOS transistors T_(P1) andT_(Y2) and the drain of the first NMOS transistor T_(N1) areelectrically connected with the rear unit.

(8) As an eighth aspect applicable to the first aspect, the front unitA_(m) may include a first gate circuit and a second gate circuit. Thefirst gate circuit outputs a signal indicating a logical NOR betweeneither one of a logically inverted signal of the control signal C_(m) orthe control signal C_(n) and the input signal I_(m). The second gatecircuit outputs a signal indicating a logical NAND between the other oneof the control signal C_(m) and the control signal C_(n), and the outputsignal of the first gate circuit.

(9) The rear unit according to a ninth aspect applicable to the seventhor eighth aspect may have a configuration capable of receiving outputsignals from the front units A₁ to A₄ of the front units A₁ to A_(M) (aconfiguration when M=4). In this case, the rear unit in theconfiguration when M=4 may include two third gate circuits G₃₁ and G₃₂,and a fourth gate circuit G₄. The third gate circuits G₃₁ and G₃₂ eachexclusively receive two signals of the output signals from the frontunits A₁ to A₄. Then, the third gate circuits G₃₁ and G₃₂ each output asignal indicating a logical NAND between the received signals. Thefourth gate circuit G₄ receives the signals output from the third gatecircuits G₃₁ and G₃₂, and outputs a signal indicating a logical NORbetween the received signals.

(10) The rear unit according to a tenth aspect applicable to the seventhor eighth aspect may have a configuration capable of receiving outputsignals from the front units A₁ to A₄ of the front units A₁ to A_(M) (aconfiguration when M=4). In this case, the rear unit in theconfiguration when M=4 may include two third gate circuits G₃₁ and G₃₂,and a fourth gate circuit G₄. The third gate circuits G₃₁ and G₃₂ eachexclusively receive two signals of the output signals from the frontunits A₁ to A₄. Then, the third gate circuits G₃₁ and G₃₂ each output asignal indicating a logical NAND between the received signals. Thefourth gate circuit G₄ receives the signals output from the third gatecircuits G₃₁ and G₃₂, and outputs a signal indicating a logical ORbetween the received signals.

(11) The rear unit according to an eleventh aspect applicable to theseventh or eighth aspect may have a configuration capable of receivingoutput signals from the front units A₁ to A₈ of the front units A₁ toA_(M) (a configuration when M=8). In this case, the rear unit in theconfiguration when M=8 may include four third gate circuits G₃₁ to G₃₄,and two fourth gate circuits G₄₁ and G₄₂. The third gate circuits G₃₁ toG₃₄ each exclusively receive two signals of the output signals from thefront units A₁ to A₈. Then, the third gate circuits G₃₁ to G₃₄ eachoutput a signal indicating a logical NAND between the received signals.The fourth gate circuit G₄₁ and G₄₂ each exclusively receive two signalsof the signals output from third gate circuits G₃₁ to G₃₄. Then, thefourth gate circuits G₄₁ and G₄₂ each output a signal indicating alogical NOR between the received signals. The fifth gate circuit G₅receives the signals output from the fourth gate circuits G₄₁ and G₄₂,and outputs a signal indicating a logical NAND between the receivedsignals.

(12) As a twelfth aspect applicable to at least any one aspect of theabove first to eleventh aspects, the signal multiplexer may furtherinclude a generation unit which generates the control signals C₁ toC_(M).

(13) The generation unit according to a thirteenth aspect applicable tothe above twelfth aspect may include a configuration (a configurationwhen M=8) for generating the control signals C₁ to C₈ corresponding tothe control signals C₁ to C_(M). In this case, the generation unit inthe configuration when M=8 may include first to fourth latch circuitsand sixth to ninth gate circuits. The sixth gate circuit outputs, as thecontrol signal C₁, a signal indicating a logical AND between a secondclock obtained by dividing a first clock by two and a third clockobtained by dividing the second clock by two. The first latch circuitreceives the control signal C₁, latches a value of the control signal C₁at a falling timing of the first clock, and outputs the latched value asthe control signal C₂. The seventh gate circuit outputs, as the controlsignal C₃, a signal indicating a logical AND between a logicallyinverted signal of the second clock and the third clock. The secondlatch circuit receives the control signal C₃, latches a value of thecontrol signal C₃ at a falling timing of the first clock, and outputsthe latched value as the control signal C₄. The eighth gate circuitoutputs, as the control signal C₅, a signal indicating a logical ANDbetween the second clock and a logically inverted signal of the thirdclock. The third latch circuit receives the control signal C₅, latches avalue of the control signal C₅ at a falling timing of the first clock,and outputs the latched value as the control signal C₆. The ninth gatecircuit outputs, as the control signal C₇, a signal indicating a logicalAND between a logically inverted signal of the second clock and alogically inverted signal of the third clock. The fourth latch circuitreceives the control signal C₇, latches a value of the control signal C₇at a falling timing of the first clock, and outputs the latched value asthe control signal C₈.

Each aspect listed in [Description of embodiment of the presentinvention] is applicable to each of the other aspects or allcombinations of the other aspects.

Details of Embodiments of the Present Invention

Hereinafter, specific configurations of a signal multiplexer accordingto the present embodiment are described in detail with reference to theattached drawings. Note that, the present invention is not limited toexamples to be described, is represented by claims, and includes allmodifications within the meaning and scope equivalent to claims. In thedescription of the drawings, identical elements are denoted by the samereference signs, and overlapped descriptions are omitted.

FIG. 1 is a diagram showing a configuration of a signal multiplexer 1according to the present embodiment. The signal multiplexer 1 in FIG. 1multiplexes M number of input signals I₁ to I_(M), and outputs oneoutput signal (multiplexed signal). Here, M is an integer defined by2^(i), and i is an integer of 2 or greater. The signal multiplexer 1outputs a signal corresponding to any input signal of the M number ofinput signals I₁ to I_(M) according to a signal level of each of Mnumber of control signals C₁ to C_(M). The signal multiplexer 1 includesM number of front units A₁ to A_(M), a rear unit B, and a generationunit 2 which generates the control signals C₁ to C_(M).

An m-th front unit A_(m) of the M number of front units A₁ to A_(M)receives an input signal I_(m) of the M number of input signals I₁ toI_(M), and a control signal C_(m), a control signal C_(n) of the Mnumber of control signals C₁ to C_(M). Here, m is an integer of 1 to M.Furthermore, n is an integer of 1 when m=M, and of m+1 when m<M. Thefront unit A_(m) outputs an output signal corresponding to the inputsignal I_(m) input from an input end 1A when both signal levels of thecontrol signal C_(m) and the control signal C_(n) are significant.Furthermore, the front unit A_(m) outputs an output signal having afixed signal level when at least one signal level of either the controlsignal C_(m) or the control signal C_(n) is non-significant(insignificant). Note that, the fixed signal level (hereinafter,referred to as a fixed level) of the output signal is either of a highlevel (hereinafter, referred to as an H-level) or a low level(hereinafter, referred to as an L-level).

The rear unit B is connected with the output ends of the front units A₁to A_(M). In FIG. 1, 1C is a signal line group which electricallyconnects the front units A₁ to A_(M) with the rear unit B. In otherwords, the front units A₁ to A_(M) are connected in parallel with therear unit B. The rear unit B receives signals output from the frontunits A₁ to A_(M), and outputs signals corresponding to the receivedsignal. Specifically, the rear unit B outputs a signal having adifferent signal level in the case in which all the signals output fromthe front units A₁ to A_(M) are the same signal level or in the othercase.

FIG. 2 is a table showing the relation of the control signals C₁ toC_(M), the output signals of the front units A₁ to A_(M), and the outputsignal of the rear unit B in the signal multiplexer 1 according to thepresent embodiment. In FIG. 2, the signals corresponding to the inputsignals I₁ to I_(M) are expressed as “I₁” to “I_(M)” respectively. Thesignals corresponding to the input signals I₁ to I_(M) are,specifically, the input signals I₁ to I_(M), the logically invertedsignals of the input signals I₁ to I_(M), and the like. “Fixed”indicates a fixed level, and means that the signal level is fixed to theH-level or the L-level. Furthermore, the terms “significant” and“non-significant” in the signal level have the logically invertedrelation in which “significant” indicates the H-level (signal “1”) when“non-significant” indicates the L-level (signal “0”) and “significant”indicates the L-level (signal “0”) when “non-significant” indicates theH-level (signal “1”).

FIG. 3 is a timing chart of the control signals C₁ to C_(M), the inputsignals I₁ to I_(M), and the output signal of the rear unit B. As shownin FIG. 3, the control signals C₁ to C_(M) are signals having M unitinterval (UI) as one period. In the control signals C₁ to C_(M), thesignificant level (signal level) of 2 UI and the non-significant level(signal level) of (M−2) UI are repeated. The control signal C_(m) isdelayed by (m−1) UI with respect to the control signal C₁. In otherwords, the control signal C₂ is delayed by 1 UI with respect to thecontrol signal C₁, the control signal C₃ is delayed by 2 UI with respectto the control signal C₁, and the control signal C_(M) is delayed by(M−1) UI with respect to the control signal C₁. Note that, the unitinterval is the unit length of an output signal of the signalmultiplexer 1. For example, when the data rate of an output signal is 40Gb/s, 1 UI is 25 ps.

Next, a configuration example of the generation unit 2 is described.

The control signals C₁ to C₄ when M=4 are signals in which thesignificant level of 2 UI and the non-significant level of 2 UI arerepeated and the time being the significant level and the time being thenon-significant level are equal. Thus, the control signal C₁ and thecontrol signal C₃ have the logically inverted relation, and the controlsignal C₂ and the control signal C₄ have the logically invertedrelation. Consequently, the generation unit 2 when M=4 can generate thecontrol signals C₁ to C₄ by, for example, including a delay circuitwhich delays a clock and a logic inverting circuit which inverts thelogic.

FIG. 4 is a diagram showing a configuration example of the generationunit 2 when M=8. As shown in FIG. 4, the generation unit 2 having theconfiguration when M=8 includes ½ frequency divider circuits 3 and 4,latch circuits L1 to L4, and gate circuits G0 to G4. The ½ frequencydivider circuit 3 includes a latch circuit L5 and a gate circuit G5. The½ frequency divider circuit 4 includes a latch circuit L6 and a gatecircuit G6. The latch circuits L1 to L6 are implemented by, for example,D flip-flop circuits.

In the ½ frequency divider circuit 3, the latch circuit L5 receives aclock CLK1 input from an input end 2A and the output signal of the gatecircuit G5, latches a value of the output signal of the gate circuit G5at a rising timing of the clock CLK1, and outputs the latched value as aclock CLK2. The clock CLK2 is a ½ frequency division signal obtained bydividing the clock CLK1 by two. The gate circuit G5 receives the clockCLK2 which is the output signal of the latch circuit L5, and outputs alogically inverted signal of the signal of the clock CLK2. According tothe ½ frequency divider circuit 3 configured in this manner, the clockCLK2 and the logically inverted signal of the clock CLK2 are generatedfrom the clock CLK1.

In the ½ frequency divider circuit 4, the latch circuit L6 receives theclock CLK2 and the output signal of the gate circuit G6, latches a valueof the output signal of the gate circuit G6 at a rising timing of theclock CLK2, and outputs the latched value as a clock CLK3. The clockCLK3 is a ½ frequency division signal obtained by dividing the clockCLK2 by two. The gate circuit G6 receives the clock CLK3 which is theoutput signal of the latch circuit L6, and outputs a logically invertedsignal of the signal of the clock CLK3. According to the ½ frequencydivider circuit 4 configured in this manner, the clock CLK3 and thelogically inverted signal of the clock CLK3 are generated from the clockCLK2.

The gate circuit G0 receives the clock CLK1, and outputs a logicallyinverted signal of the clock CLK1.

The gate circuit G1 receives the clock CLK2 and the clock CLK3, andoutputs a signal indicating a logical AND between the received signalsas the control signal C₁. Specifically, the gate circuit G1 includes agate circuit G1A which receives the clock CLK2 and the clock CLK3 andoutputs a signal indicating a logical NAND between the received signals,and a gate circuit G1B which receives the output signal of the gatecircuit G1A and outputs a logically inverted signal of the receivedsignal as the control signal C₁.

The latch circuit L1 receives the logically inverted signal of the clockCLK1 and the control signal C₁, latches a value of the control signal C₁at a rising timing of the logically inverted signal of the clock CLK1,and outputs the latched value as the control signal C₂. The latchcircuit L1 is equivalent to a circuit which latches a value of thecontrol signal C₁ at a falling timing of the clock CLK1.

The gate circuit G2 receives the logically inverted signal of the clockCLK2 and the clock CLK3, and outputs a signal indicating a logical ANDbetween the received signals as the control signal C₃. Specifically, thegate circuit G2 includes a gate circuit G2A which receives the logicallyinverted signal of the clock CLK2 and the clock CLK3 and outputs asignal indicating a logical NAND between the received signals, and agate circuit G2B which receives the output signal of the gate circuitG2A and outputs a logically inverted signal of the received signal asthe control signal C₃.

The latch circuit L2 receives the logically inverted signal of the clockCLK1 and the control signal C₃, latches a value of the control signal C₃at a rising timing of the logically inverted signal of the clock CLK1,and outputs the latched value as the control signal C₄. The latchcircuit L2 is equivalent to a circuit which latches a value of thecontrol signal C₃ at a falling timing of the clock CLK1.

The gate circuit G3 receives the clock CLK2 and the logically invertedsignal of the clock CLK3, and outputs a signal indicating a logical ANDbetween the received signals as the control signal C₅. Specifically, thegate circuit G3 includes a gate circuit G3A which receives the clockCLK2 and the logically inverted signal of the clock CLK3 and outputs asignal indicating a logical NAND between the received signals, and agate circuit G3B which receives the output signal of the gate circuitG3A and outputs a logically inverted signal of the received signal asthe control signal C₅.

The latch circuit L3 receives the logically inverted signal of the clockCLK1 and the control signal C₅, latches a value of the control signal C₅at a rising timing of the logically inverted signal of the clock CLK1,and outputs the latched value as the control signal C₆. The latchcircuit L3 is equivalent to the circuit which latches a value of thecontrol signal C₅ at a falling timing of the clock CLK1.

The gate circuit G4 receives the logically inverted signal of the clockCLK2 and the logically inverted signal of the clock CLK3, and outputs asignal indicating a logical AND between the received signals as thecontrol signal C₇. Specifically, the gate circuit G4 includes a gatecircuit G4A which receives the logically inverted signal of the clockCLK2 and the logically inverted signal of the clock CLK3 and outputs asignal indicating a logical NAND between the received signals, and agate circuit G4B which receives the output signal of the gate circuitG4A and outputs a logically inverted signal of the received signal asthe control signal C₇.

The latch circuit L4 receives the logically inverted signal of the clockCLK1 and the control signal C₇, latches a value of the control signal C₇at a rising timing of the logically inverted signal of the clock CLK1,and outputs the latched value as the control signal C₈. The latchcircuit L4 is equivalent to a circuit which latches a value of thecontrol signal C₇ at a falling timing of the clock CLK1.

FIG. 5 is a timing chart of the clock CLK1, the logically invertedsignal of the clock CLK1, the clock CLK2, the clock CLK3, and thecontrol signals C₁ to C₈ when M=8.

The generation unit 2 configured in the above manner can generate thecontrol signals C₁ to C₈ in which the significant level of 2 UI and thenon-significant level of 6 UI are repeated.

Note that, since the control signals C₁ to C_(M) are equivalent toM-phase clocks in which the duty ratio is 2/M and the phase is shiftedby 2π/M, any one of signals output from the generation unit 2 as thecontrol signals C₁ to C_(M) may be the control signal C₁, and thecontrol signals C₂ to C_(M) are only required to be selected so as to besignals delayed by 1 UI to (M−1) UI respectively with respect to thecontrol signal C₁. Specifically, for example, the output signal of thelatch circuit L1 may be the control signal C₁ instead of being theoutput signal of the gate circuit G1 as the control signal C₁. In thiscase, the control signals C₂ to C₈ are only required to be selected soas to be signals delayed by 1 UI to 7 UI respectively with respect tothe control signal C₁. Furthermore, the generation unit 2 may receive,for example, the clock CLK2 and the clock CLK3 externally. Moreover, thegeneration unit 2 may receive the clock CLK2 or the clock CLK3externally and generate a logically inverted signal of the receivedclock.

Next, configuration examples of the front unit A_(m) and the rear unit Bwhen the fixed level is the L-level are described with reference toFIGS. 6 to 10.

FIG. 6 is a diagram showing a first configuration example of the frontunit A_(m). As shown in FIG. 6, the first configuration example of thefront unit A_(m) includes three PMOS transistors T_(P1) to T_(Y3)(included in a first transistor group) connected in series and two NMOStransistors T_(N1) and T_(N2) (included in a second transistor group)connected in parallel. The three PMOS transistors T_(P1) to T_(P3) andthe two NMOS transistors T_(N1) and T_(N2) are connected in series, andits connecting point J is further connected with the rear unit B (seeFIG. 1). The end part opposite to the connecting point J of the threePMOS transistors T_(P1) to T_(P3) is connected with a power source (anupper-limit reference end T1 set to upper-limit potential), and the endparts of the two NMOS transistors T_(N1) and T_(N2) opposite to theconnecting point J are connected with the grounds (a first lower-limitreference end T2 set to first lower-limit potential and a secondlower-limit reference end T3 set to second lower-limit potential). Notethat, an output end 1C_(m) of the front unit A_(m) is included in thesignal line group 1C electrically connecting the front units A₁ to A_(M)with the rear unit B.

Any one of the input signal I_(m), the control signal C_(m), and thecontrol signal C_(n) is exclusively input to the gate of each of thethree PMOS transistors T_(P1) to T_(P3). Note that, in the example ofFIG. 6, the input signal I_(m) is input to the gate of the PMOStransistor T_(P1), the control signal C_(m) is input to the gate of thePMOS transistor T_(P2), and the control signal C_(n) is input to thegate of the PMOS transistor T_(P3).

As shown in FIG. 3, after the input signal I_(m) is output, the signalshaving the significant levels are output in the order of the controlsignal C_(m) and the control signal C_(n). Thus, when all the three PMOStransistors T_(P1) to T_(P3) shown in FIG. 6 are turned ON, the PMOStransistors are necessarily turned ON sequentially from the PMOStransistor farthest from the connecting point J. Consequently, it ispossible to suppress the delay compared with, for example, the case inwhich the PMOS transistor farthest from the connecting point J is turnedON last.

Either one of the control signal C_(m) or the control signal C_(n) isexclusively input to the gate of each of the two NMOS transistors T_(N1)and T_(N2). In the example of FIG. 6, the control signal C_(m) is inputto the gate of the NMOS transistor T_(N1), and the control signal C_(n)is input to the gate of the NMOS transistor T_(N2).

The significant levels of the control signal C_(m) and the controlsignal C_(n) are the L-levels, and the non-significant levels are theH-levels. Thus, in the first configuration example of the front unitA_(m), when the control signal C_(m) is the L-level and the controlsignal C_(n) is the L-level, the input signal I_(m) is output as thesignal corresponding to the input signal I_(m). On the other hand, whenthe control signal C_(m) is the H-level or the control signal C_(n) isthe H-level, a signal having a voltage level of the ground is output asthe signal having the L-level.

FIG. 7 is a diagram showing a second configuration example of the frontunit A_(m). As shown in FIG. 7, the second configuration example of thefront unit A_(m) includes a gate circuit G₁ and a gate circuit G₂. Thegate circuit G₁ receives two of an input signal I_(m), a control signalC_(m), and a control signal C_(n), and outputs a signal indicating alogical NAND between the received signals. In the example of FIG. 7, thegate circuit G₁ receives the input signal I_(m) and the control signalC_(m), and outputs a signal indicating a logical NAND between thereceived signals.

The gate circuit G₂ receives the output signal of the gate circuit G₁,and the logically inverted signal of the other one of the input signalI_(m), the control signal C_(m), and the control signal C_(n), andoutputs a signal indicating a logical NOR between the received signals.In the example of FIG. 7, the gate circuit G₂ receives the output signalof the gate circuit G₁ and the logically inverted signal of the controlsignal C_(n) and outputs a signal indicating a logical NOR between thereceived signals. Specifically, the gate circuit G₂ includes the gatecircuit G_(2A) which receives the control signal C_(n) and outputs alogically inverted signal thereof, and the gate circuit G_(2B) whichreceives the output signal of the gate circuit GA and the output signalof the gate circuit G₁ and outputs a signal indicating a logical NORbetween the received signals.

The significant levels of the control signal C_(m) and the controlsignal C_(n) are the H-levels, and the non-significant levels are theL-levels. Thus, in the second configuration example of the front unitA_(m), when the control signal C_(m) is the H-level and the controlsignal C_(n) is the H-level, the input signal I_(m) is output as thesignal corresponding to the input signal I_(m). On the other hand, whenthe control signal C_(m) is the L-level or the control signal C_(n) isthe L-level, a signal having a voltage level of the ground is output asthe signal having the L-level.

FIG. 8 is a diagram showing a first configuration example of the rearunit B. As shown in FIG. 8, the first configuration example of the rearunit B is a configuration example when M=4, and includes two gatecircuits G₃₁ and G₃₂ and a gate circuit G₄. The two gate circuits G₃₁and G₃₂ each exclusively receive two signals of the signals output fromthe four front units A₁ to A₄, and each output a signal indicating alogical NOR between the received signals. In the example of FIG. 8, thegate circuit G₃₁ receives the input signal I_(m) and the signal havingthe L-level, and outputs a logically inverted signal of the input signalI_(m). The gate circuit G₃₂ receives two signals having the L-levels,and outputs a signal having the H-level.

The gate circuit G₄ receives the signals output from the two gatecircuits G₃₁ and G₃₂, and outputs a signal indicating a logical NANDbetween the received signals. In the example of FIG. 8, the gate circuitG₄ receives the logically inverted signal of the input signal I_(m) fromthe gate circuit G₃₁, receives the signal having the H-level from thegate circuit G₃₂, and outputs the input signal I_(m). As describedabove, the first configuration example of the rear unit B receives theinput signal I_(m) and three signals having the L-levels output from thefour front units A₁ to A₄, and outputs the input signal I_(m).

FIG. 9 is a diagram showing a second configuration example of the rearunit B. As shown in FIG. 9, the second configuration example of the rearunit B is a configuration example when M=4, and includes two gatecircuits G₃₁ and G₃₂ and a gate circuit G₄. The two gate circuits G₃₁and G₃₂ have the same configurations as those of the two gate circuitsG₃₁ and G₃₂ of the first configuration example of the rear unit B.

The gate circuit G₄ receives the signals output from the two gatecircuits G₃₁ and G₃₂, and outputs a signal indicating a logical ANDbetween the received signal. Specifically, the gate circuit G₄ includesthe gate circuit G_(4A) and the gate circuit G_(4B) which eachexclusively receive either one of the signals output from the two gatecircuits G₃₁ and G₃₂, and each output the logically inverted signal ofthe received signal, and a gate circuit G_(4C) which receives thesignals output from the gate circuit G_(4A) and the gate circuit G_(4B)and outputs a signal indicating a logical NOR between the receivedsignals.

In the example of FIG. 9, the gate circuit G_(4A) receives the logicallyinverted signal of the input signal I_(m) from the gate circuit G₃₁, andoutputs the input signal I_(m). The gate circuit G_(4B) receives thesignal having the H-level from the gate circuit G₃₂, and outputs asignal having the L-level. The gate circuit G_(4C) receives the inputsignal I_(m) from the gate circuit G₃₁, receives the signal having theL-level from the gate circuit G₃₂, and outputs a logically invertedsignal of the input signal I_(m).

As described above, the second configuration example of the rear unit Breceives the input signal I_(m) and three signals having the L-levelsoutput from the four front units A₁ to A₄, and outputs a logicallyinverted signal of the input signal I_(m). Note that, the two gatecircuits G₃₁ and G₃₂ may output a signal indicating a logical OR betweenthe received signals, and the gate circuit G₄ may output a signalindicating a logical NOR between the received signals.

FIG. 10 is a diagram showing a third configuration example of the rearunit B. As shown in FIG. 10, the third configuration example of the rearunit B is a configuration example when M=8, and includes four gatecircuits G₃₁ to G₃₄, two gate circuits G₄₁ and G₄₂, and a gate circuitG₅. The four gate circuits G₃₁ and G₃₄ each exclusively receive twosignals of the signals output from the eight front units A₁ to A₈, andeach output a signal indicating a logical NOR between the receivedsignals. In the example of FIG. 10, the gate circuit G₃₁ receives theinput signal I_(m) and the signal having the L-level, and outputs alogically inverted signal of the input signal I_(m). The gate circuitsG₃₂ to G₃₄ each receive two signals having the L-levels, and each outputa signal having the H-level.

The two gate circuits G₄₁ and G₄₂ each exclusively receive two signalsof the signals output from the four gate circuits G₃₁ to G₃₄, and eachoutput a signal indicating a logical NAND between the received signals.In the example of FIG. 10, the gate circuit G₄₁ receives the logicallyinverted signal of the input signal I_(m) from the gate circuit G₃₁,receives the signal having the H-level from the gate circuit G₃₂, andoutputs the input signal I_(m). The gate circuit G₄₂ receives thesignals having the H-levels from the gate circuit G₃₃ and the gatecircuit G₃₄, and outputs a signal having the L-level.

The gate circuit G₅ receives the signals output from the two gatecircuits G₄₁ and G₄₂, and outputs a signal indicating a logical NORbetween the received signals. In the example of FIG. 10, the gatecircuit G₅ receives the input signal I_(m) from the gate circuit G₄₁,receives the signal having the L-level from the gate circuit G₄₂, andoutputs a logically inverted signal of the input signal I_(m). Asdescribed above, the third configuration example of the rear unit Breceives the input signal I_(m) and seven signals having the L-levelsfrom the eight front units A₁ to A₈, and outputs a logically invertedsignal of the input signal I_(m).

Next, configuration examples of the front unit A_(m) and the rear unit Bwhen the fixed level is the H-level are described with reference toFIGS. 11 to 15.

FIG. 11 is a diagram showing a third configuration example of the frontunit A_(m). As shown in FIG. 11, the third configuration example of thefront unit A_(m) includes three NMOS transistors T_(N1) to T_(N3)(included in a second transistor group) connected in series and two PMOStransistors T_(P1) and T_(P2) (included in a first transistor group)connected in parallel. The three NMOS transistors T_(N1) to T_(N3) andthe two PMOS transistors T_(P1) and T_(P2) are connected in series, andits connecting point J is further connected with the rear unit B (seeFIG. 1). The end part opposite to the connecting point J of the threeNMOS transistors T_(N1) to T_(N3) is connected with a ground (alower-limit reference end T2 set to lower-limit potential), and the endparts of the two PMOS transistors T_(P1) and T_(P2) opposite to theconnecting point J are connected with the power sources (a firstupper-limit reference end T1 set to first upper-limit potential and asecond upper-limit reference end T4 set to second upper-limitpotential).

Any one of the input signal I_(m), the control signal C_(m), and thecontrol signal C_(n) is exclusively input to the gate of each of thethree NMOS transistors T_(N1) to T_(N3). In the example of FIG. 11, thecontrol signal C_(n) is input to the gate of the NMOS transistor T_(N1),the control signal C_(m) is input to the gate of the NMOS transistorT_(N2), and the input signal I_(m) is input to the gate of the NMOStransistor T_(N3).

As shown in FIG. 3, after the input signal I_(m) is output, the signalshaving the significant levels are output in the order of the controlsignal C_(m) and the control signal C_(n). Thus, when all the three NMOStransistors T_(N1) to T_(N3) shown in FIG. 11 are turned ON, the NMOStransistors are necessarily turned ON sequentially from the NMOStransistor farthest from the connecting point J. Consequently, it ispossible to suppress the delay compared with, for example, the case inwhich the NMOS transistor farthest from the connecting point J is turnedON last.

Either one of the control signal C_(m) or the control signal C_(n) isexclusively input to the gate of each of the two PMOS transistors T_(P1)and T_(P2). Here, the control signal C_(m) is input to the gate of thePMOS transistor T_(P1), and the control signal C_(n) is input to thegate of the PMOS transistor T_(P2).

The significant levels of the control signal C_(m) and the controlsignal C_(n) are the H-levels, and the non-significant levels are theL-levels. Thus, in the third configuration example of the front unitA_(m), when the control signal C_(m) is the H-level and the controlsignal C_(n) is the H-level, the input signal I_(m) is output as thesignal corresponding to the input signal I_(m). On the other hand, whenthe control signal C_(m) is the L-level or the control signal C_(n) isthe L-level, a signal having a voltage level of the power supply isoutput as the signal having the H-level.

FIG. 12 is a diagram showing a fourth configuration example of the frontunit A_(m). As shown in FIG. 12, the fourth configuration example of thefront unit A_(m) includes a gate circuit G₁ and a gate circuit G₂. Thegate circuit G₁ outputs a signal indicating a logical NOR between of alogically inverted signal of either one of the control signal C_(m) orthe control signal C_(n) and the input signal I_(m). In the example ofFIG. 12, the gate circuit G₁ receives the logically inverted signal ofthe control signal C_(m) and the input signal I_(m), and outputs alogically inverted signal of the input signal I_(m). Specifically, thegate circuit G₁ includes the gate circuit G_(1A) which receives thecontrol signal C_(m) and outputs a logically inverted signal thereof,and the gate circuit G_(2B) which receives the output signal of the gatecircuit G_(1A) and the input signal I_(m) and outputs a signalindicating a logical NAND between the received signals.

The gate circuit G₂ receives the other one of the control signal C_(m)and the control signal C_(n), and the output signal of the gate circuitG₁, and outputs a signal indicating a logical NAND between the receivedsignals. In the example of FIG. 12, the gate circuit G₂ receives thecontrol signal C_(n) and the output signal of the gate circuit G₁, andoutputs a signal indicating a logical NAND between the received signals.

The significant levels of the control signal C_(m) and the controlsignal C_(n) are the H-levels, and the non-significant levels are theL-levels. Thus, in the fourth configuration example of the front unitA_(m), the input signal I_(m) is output as the signal corresponding tothe input signal I_(m) when the control signal C_(m) is the H-level andthe control signal C_(n) is the H-level, and the signal having a voltagelevel of the power source is output as the signal having the H-levelwhen the control signal C_(m) is the L-level or the control signal C_(n)is the L-level.

FIG. 13 is a diagram showing a fourth configuration example of the rearunit B. As shown in FIG. 13, the fourth configuration example of therear unit B is a configuration example when M=4, and includes two gatecircuits G₃₁ and G₃₂ and a gate circuit G₄. The two gate circuits G₃₁and G₃₂ each exclusively receive two signals of the signals output fromthe four front units A₁ to A₄, and each output a signal indicating alogical NAND between the received signals. In the example of FIG. 13,the gate circuit G₃₁ receives the input signal I_(m) and the signalhaving the H-level, and outputs a logically inverted signal of the inputsignal I_(m). Furthermore, the gate circuit G₃₂ receives two signalshaving the H-levels, and outputs a signal having the L-level.

The gate circuit G₄ receives the signals output from the two gatecircuits G₃₁ and G₃₂, and outputs a signal indicating a logical NORbetween the received signals. In the example of FIG. 13, the gatecircuit G₄ receives the logically inverted signal of the input signalI_(m) from the gate circuit G₃₁, receives the signal having the L-levelfrom the gate circuit G₃₂, and outputs the input signal I_(m). Asdescribed above, the fourth configuration example of the rear unit Breceives the input signal I_(m) output from the four front units A₁ toA₄ and three signals having the L-levels, and outputs the input signalI_(m).

FIG. 14 is a diagram showing a fifth configuration example of the rearunit B. As shown in FIG. 14, the fifth configuration example of the rearunit B is a configuration example when M=4, and includes two gatecircuits G₃₁ and G₃₂ and a gate circuit G₄. The two gate circuits G₃₁and G₃₂ have the same configurations as those of the two gate circuitsG₃₁ and G₃₂ of the fourth configuration example of the rear unit B.

The gate circuit G₄ receives the signals output from the two gatecircuits G₃₁ and G₃₂, and outputs a signal indicating a logical ORbetween the received signals. Specifically, the gate circuit G₄ includesthe gate circuit G_(4A) and the gate circuit G_(4B) which eachexclusively receive either one of the signals output from the two gatecircuits G₃₁ and G₃₂, and each output a logically inverted signal of thereceived signal, and the gate circuit G_(4C) which receives the signalsoutput from the gate circuit G_(4A) and the gate circuit G_(4B) andoutputs a signal indicating a logical NOR between the received signals.

In the example of FIG. 14, the gate circuit G_(4A) receives thelogically inverted signal of the input signal I_(m) from the gatecircuit G₃₁, and outputs the input signal I_(m). The gate circuit G_(4B)receives the signal having the L-level from the gate circuit G₃₂, andoutputs a signal having the H-level. The gate circuit G_(4C) receivesthe input signal I_(m) from the gate circuit G₃₁, receives the signalhaving the H-level from the gate circuit G₃₂, and outputs a logicallyinverted signal of the input signal I_(m).

As described above, the fifth configuration example of the rear unit Breceives the input signal I_(m) output from the four front units A₁ toA₄ and three signals having the H-levels, and outputs a logicallyinverted signal of the input signal I_(m). Note that, the two gatecircuits G₃₁ and G₃₂ may output a signal indicating a logical ANDbetween the received signals, and the gate circuit G₄ may output asignal indicating a logical NAND between the received signals.

FIG. 15 is a diagram showing a sixth configuration example of the rearunit B. As shown in FIG. 15, the sixth configuration example of the rearunit B is a configuration example when M=8, and includes four gatecircuits G₃₁ to G₃₄, two gate circuits G₄₁ and G₄₂, and a gate circuitG₅. The four gate circuits G₃₁ to G₃₄ each exclusively receive twosignals of the signals output from the eight front units A₁ to A₈, andeach output a signal indicating a logical NAND between the receivedsignals. In the example of FIG. 15, the gate circuit G₃₁ receives theinput signal I_(m) and the signal having the H-level, and outputs alogically inverted signal of the input signal I_(m). The gate circuitsG₃₂ to G₃₄ each receive two signals having the H-levels, and each outputa signal having the L-level.

The two gate circuits G₄₁ and G₄₂ each exclusively receive two signalsof the signals output from the four gate circuits G₃₁ to G₃₄, and eachoutput a signal indicating a logical NOR between the received signals.In the example of FIG. 15, the gate circuit G₄₁ receives the logicallyinverted signal of the input signal I_(m) from the gate circuit G₃₁,receives the signal having the L-level from the gate circuit G₃₂, andoutputs the input signal I_(m). The gate circuit G₄₂ receives thesignals having the L-levels from the gate circuit G₃₃ and the gatecircuit G₃₄, and outputs a signal having the H-level.

The gate circuit G₅ receives the signals output from the two gatecircuits G₄₁ and G₄₂, and outputs a signal indicating a logical NANDbetween the received signals. In the example of FIG. 15, the gatecircuit G₅ receives the input signal I_(m) from the gate circuit G₄₁,receives the signal having the H-level from the gate circuit G₄₂, andoutputs a logically inverted signal of the input signal I_(m). Asdescribed above, the sixth configuration example of the rear unit Breceives the input signal I_(m) and seven signals having the H-levelsfrom the eight front units A₁ to A₈, and outputs a logically invertedsignal of the input signal I_(m).

As described above, the first and fourth configuration examples of therear unit B receive the input signal I_(m) and (M−1) number of signalshaving the fixed levels from M number of front units A₁ to A_(M), andoutputs the input signal I_(m). Furthermore, the second, third, fifth,and sixth configuration examples of the rear unit B receive the inputsignal I_(m) and (M−1) number of signals having the fixed levels fromthe M number of front units A₁ to A_(M), and outputs a logicallyinverted signal of the input signal I_(m). Thus, the above configurationexamples of the rear unit B output a signal having a different signallevel in the case in which all the signal output from the M number offront units A₁ to A_(M) are the same signal level or in the other case.

In the signal multiplexer 1 according to the above present embodiment,there is no configuration in which all output ends of the M number offront units A₁ to A_(M) are connected with one connecting point. Thus,the signal multiplexer 1 can suppress the increase of the load capacityvalue and sufficiently accelerate the data rate compared with such aconfiguration having a multiplexed connecting point.

Furthermore, in the signal multiplexer disclosed in Non-PatentLiterature 1, the parasitic resistance value and parasitic capacityvalue are high because two transfer gates are connected in series. Forthis reason, the waveform of an output signal becomes dull, and thefrequency band is restricted. Thus, it is not possible to sufficientlyaccelerate the data rate.

In contrast, in the above configuration examples of the front unitA_(m), there is no configuration in which two switches are connected inseries. Thus, the parasitic resistance value and parasitic capacityvalue due to the switches become low, and it is possible to suppress thedullness of the waveform of an output signal. Consequently, it ispossible to extend the frequency band. Thus, according to the signalmultiplexer 1, it is possible to sufficiently accelerate the data rate.Furthermore, according to the signal multiplexer 1, it is possible tomitigate what is called a charge sharing effect. The charge sharingeffect is a phenomenon in which the parasitic capacity is charged anddischarged through a switch for turning ON a buffer section outputting ahigh impedance, and the waveform of an output signal thereby becomesdull.

Comparing the first to fourth configuration examples of the front unitA_(m), in the first and third configuration examples, the number of gatecircuits to be driven is fewer than that in the second and fourthconfiguration examples. For this reason, the first and thirdconfiguration examples can suppress the power consumption and delay.

Comparing the first configuration example of the front unit A_(m) withthe third configuration example, while the three PMOS transistors T_(P1)to T_(P3) are connected in series in the first configuration example,the three NMOS transistors T_(N1) to T_(N3) are connected in series inthe third configuration example. Thus, in terms of the data rate, thefirst configuration example has an advantage compared with the thirdconfiguration example.

Comparing the first to sixth configuration examples of the rear unit B,while the last stage having the fastest data rate is a logical NAND inthe first, fifth, and sixth configuration examples, the last stagehaving the fastest data rate is a logical NOR in the second, third, andfourth configuration examples. Generally, the data rate is faster in alogical NAND than in a logical NOR. Thus, in this point, the first,fifth, and sixth configuration examples have an advantage compared withthe second, third, and fourth configuration examples.

The present invention is not limited to the above embodiments, andvarious modification can be made. For example, the circuitconfigurations of the front units A₁ to A_(M) and the rear unit B arenot limited to the above configuration examples, and may be variousconfigurations.

As described above, according to the signal multiplexer according to thepresent embodiment, it is possible to sufficiently accelerate the datarate.

What is claimed is:
 1. A signal multiplexer which outputs a signalcorresponding to an input signal I_(m) of M number of input signals I₁to I_(M) sequentially designated based on a combination of signal levelsof an m-th control signal C_(m) and an n-th control signal C_(n) whichare selected from M number of control signals C₁ to C_(M), where M is aninteger defined by 2^(i), i is an integer of 2 or greater, m is aninteger of 1 to M, and n is an integer of 1 when m=M, and of m+1 whenm<M, while the combination of the signal levels are being maintained,the signal multiplexer comprising: M number of front units A₁ to A_(M)corresponding to the M number of input signals I₁ to I_(M), wherein anm-th front unit A_(m) of the M number of front units A₁ to A_(M) outputsan output signal corresponding to the input signal I_(m) input to thefront unit A_(m) when both signal levels of the control signal C_(m) andthe control signal C_(n) are significant, and outputs an output signalhaving a fixed signal level when at least either signal level of thecontrol signal C_(m) or the control signal C_(n) is non-significant; anda rear unit electrically connected with output ends of the front unitsA₁ to A_(M) configured to receive the output signals from the frontunits A₁ to A_(M) and output, as the signal corresponding to the inputsignal I_(m), a signal having a different signal level in a case inwhich all the output signals from the front units A₁ to A_(M) are thesame signal level or in the other case.
 2. The signal multiplexeraccording to claim 1, wherein the front unit A_(m) comprises: a firsttransistor group including a first PMOS transistor T_(P1) having asource electrically connected with an upper-limit reference end set toupper-limit reference potential, a gate, and a drain, a second PMOStransistor T_(P2) having a source electrically connected with the drainof the first PMOS transistor, a gate, and a drain, and a third PMOStransistor T_(P3) having a source electrically connected with the drainof the second PMOS transistor, a gate, and a drain, in which any one ofthe input signal I_(m), the control signal C_(m), and the control signalC_(n) is exclusively input to the gate of each of the first to thirdPMOS transistors T_(P1) to T_(P3); and a second transistor groupincluding a first NMOS transistor T_(N1) having a drain electricallyconnected with the drain of the third PMOS transistor T_(P3), a gate,and a source electrically connected with a first lower-limit referenceend set to first lower-limit reference potential lower than theupper-limit reference potential, and a second NMOS transistor T_(N2)having a drain electrically connected with the drain of the third PMOStransistor T_(P3), a gate, and a source electrically connected with asecond lower-limit reference end set to second lower-limit referencepotential lower than the upper-limit reference potential, in whicheither one of the control signal C_(m) or the control signal C_(n) isexclusively input to the gate of each of the first and second NMOStransistors T_(N1) and T_(N2), and connecting points of the drain of thethird PMOS transistor T_(P3), and the drains of the first and secondNMOS transistors T_(N1) and T_(N2) are electrically connected with therear unit.
 3. The signal multiplexer according to claim 1, wherein thefront unit A_(m) comprises: a first gate circuit configured to output asignal indicating a logical NAND between two of the input signal I_(m),the control signal C_(m), and the control signal C_(n); and a secondgate circuit configured to output a signal indicating a logical NORbetween the output signal of the first gate circuit and a logicallyinverted signal of the other one of the input signal I_(m), and thecontrol signal C_(m), and the control signal C_(n).
 4. The signalmultiplexer according to claim 2, wherein the rear unit, in order toreceive output signals from the front units A₁ to A₄ of the front unitsA₁ to A_(M), comprises: two third gate circuits G₃₁ and G₃₂ configuredto each exclusively receive two signals of the output signals from thefront units A₁ to A₄, and each output a signal indicating a logical NORbetween the received signals; and a fourth gate circuit G₄ configured toreceive the signals output from the two third gate circuits G₃₁ and G₃₂,and output a signal indicating a logical NAND between the receivedsignals.
 5. The signal multiplexer according to claim 2, wherein therear unit, in order to receive output signals from the front units A₁ toA₄ of the front units A₁ to A_(M), comprises: two third gate circuitsG₃₁ and G₃₂ configured to each exclusively receive two signals of theoutput signals from the front units A₁ to A₄, and each output a signalindicating a logical NOR between the received signals; and a fourth gatecircuit G₄ configured to receive the signals output from the two thirdgate circuits G₃₁ and G₃₂, and output a signal indicating a logical ANDbetween the received signals.
 6. The signal multiplexer according toclaim 1, wherein the rear unit, in order to receive output signals fromthe front units A₁ to A₈ of the front units A₁ to A_(M), comprises: fourthird gate circuits G₃₁ to G₃₄ configured to each exclusively receivetwo signals of the output signals from the front units A₁ to A₈, andeach output a signal indicating a logical NOR between the receivedsignals; two fourth gate circuits G₄₁ and G₄₂ configured to eachexclusively receive two signals of the signals output from the thirdgate circuits G₃₁ to G₃₄, and each output a signal indicating a logicalNAND between the received signals; and a fifth gate circuit G₅configured to receive the signals output from the two fourth gatecircuits G₄₁ and G₄₂, and output a signal indicating a logical NORbetween the received signals.
 7. The signal multiplexer according toclaim 1, wherein the front unit A_(m) comprises: a first transistorgroup including a first PMOS transistor T_(P1) having a sourceelectrically connected with a first upper-limit reference end set tofirst upper-limit reference potential, a gate, and a drain, and a secondPMOS transistor T_(P2) having a source electrically connected with asecond upper-limit reference end set to second upper-limit referencepotential, a gate, and a drain, in which either one of the controlsignal C_(m) or the control signal C_(n) is exclusively input to thegate of each of the first and second PMOS transistors T_(P1) and T_(P2);and a second transistor group including a first NMOS transistor T_(N1)having a drain electrically connected with the drains of the first andsecond PMOS transistors T_(P1) and T_(P2), a gate, and a source, asecond NMOS transistor T_(N2) having a drain electrically connected withthe source of the first NMOS transistor T_(N1), a gate, and a source,and a third NMOS transistor T_(N3) having a drain electrically connectedwith the source of the second NMOS transistor T_(N2), a gate, and asource connected with a lower-limit reference end set to lower-limitreference potential lower than the first and second upper-limitreference potential, in which, any one of the input signal I_(m), thecontrol signal C_(m), and the control signal C_(n) is exclusively inputto the gate of each of the first to third NMOS transistors T_(N1) toT_(N3), and connecting points between the drains of the first and secondPMOS transistors T_(P1) and T_(P2) and the drain of the first NMOStransistor T_(N1) are electrically connected with the rear unit.
 8. Thesignal multiplexer according to claim 1, wherein the front unit A_(m)comprises: a first gate circuit configured to output a signal indicatinga logical NOR between a logically inverted signal of either one of thecontrol signal C_(m) or the control signal C_(n), and the input signalI_(m); and a second gate circuit configured to output a signalindicating a logical NAND between the other one of the control signalC_(m) and the control signal C_(n), and the output signal of the firstgate circuit.
 9. The signal multiplexer according to claim 7, whereinthe rear unit, in order to receive output signals from the front unitsA₁ to A₄ of the front units A₁ to A_(M), comprises: two third gatecircuits G₃₁ and G₃₂ configured to each exclusively receive two signalsof the output signals from the front units A₁ to A₄, and each output asignal indicating a logical NAND between the received signals; and afourth gate circuit G₄ configured to receive the signals output from thetwo third gate circuits G₃₁ and G₃₂, and output a signal indicating alogical NOR between the received signals.
 10. The signal multiplexeraccording to claim 7, wherein the rear unit, in order to receive outputsignals from the front units A₁ to A₄ of the front units A₁ to A_(M),comprises: two third gate circuits G₃₁ and G₃₂ configured to eachexclusively receive two signals of the output signals from the frontunits A₁ to A₄, and each output a signal indicating a logical NANDbetween the received signals; and a fourth gate circuit G₄ configured toreceive the signals output from the two third gate circuits G₃₁ and G₃₂,and output a signal indicating a logical OR between the receivedsignals.
 11. The signal multiplexer according to claim 7, wherein therear unit, in order to receive output signals from the front units A₁ toA₈ of the front units A₁ to A_(M), comprises: four third gate circuitsG₃₁ to G₃₄ configured to each exclusively receive two signals of theoutput signals from the front units A₁ to A₈, and each output a signalindicating a logical NAND between the received signals; two fourth gatecircuits G₄₁ and G₄₂ configured to each exclusively receive two signalsof the signals output from the third gate circuits G₃₁ to G₃₄, and eachoutput a signal indicating a logical NOR between the received signals;and a fifth gate circuit G₅ configured to receive the signals outputfrom the fourth gate circuits G₄₁ and G₄₂, and output a signalindicating a logical NAND between the received signals.
 12. The signalmultiplexer according to claim 1, further comprising a generation unitconfigured to generate the control signals C₁ to C_(M).
 13. The signalmultiplexer according to claim 12, wherein the generation unit, in orderto generate control signals C₁ to C₈ corresponding to the controlsignals C₁ to C_(M), comprises: first to fourth latch circuits; andsixth to ninth gate circuits, the sixth gate circuit outputs, as thecontrol signal C₁, a signal indicating a logical AND between a secondclock obtained by dividing a first clock by two, and a third clockobtained by diving the second clock by two, the first latch circuitreceives the control signal C₁, latches a value of the control signal C₁at a falling timing of the first clock, and outputs the latched value asthe control signal C₂, the seventh gate circuit outputs, as the controlsignal C₃, a signal indicating a logical AND between a logicallyinverted signal of the second clock and the third clock, the secondlatch circuit receives the control signal C₃, latches a value of thecontrol signal C₃ at a falling timing of the first clock, and outputsthe latched value as the control signal C₄, the eighth gate circuitoutputs, as the control signal C₅, a signal indicating a logical ANDbetween the second clock and a logically inverted signal of the thirdclock, the third latch circuit receives the control signal C₅, latches avalue of the control signal C₅ at a falling timing of the first clock,and outputs the latched value as the control signal C₆, the ninth gatecircuit outputs, as the control signal C₇, a signal indicating a logicalAND between a logically inverted signal of the second clock and alogically inverted signal of the third clock, and the fourth latchcircuit receives the control signal C₇, latches a value of the controlsignal C₇ at a falling timing of the first clock, and outputs thelatched value as the control signal C₈.
 14. The signal multiplexeraccording to claim 3, wherein the rear unit, in order to receive outputsignals from the front units A₁ to A₄ of the front units A₁ to A_(M),comprises: two third gate circuits G₃₁ and G₃₂ configured to eachexclusively receive two signals of the output signals from the frontunits A₁ to A₄, and each output a signal indicating a logical NORbetween the received signals; and a fourth gate circuit G₄ configured toreceive the signals output from the two third gate circuits G₃₁ and G₃₂,and output a signal indicating a logical NAND between the receivedsignals.
 15. The signal multiplexer according to claim 3, wherein therear unit, in order to receive output signals from the front units A₁ toA₄ of the front units A₁ to A_(M), comprises: two third gate circuitsG₃₁ and G₃₂ configured to each exclusively receive two signals of theoutput signals from the front units A₁ to A₄, and each output a signalindicating a logical NOR between the received signals; and a fourth gatecircuit G₄ configured to receive the signals output from the two thirdgate circuits G₃₁ and G₃₂, and output a signal indicating a logical ANDbetween the received signals.
 16. The signal multiplexer according toclaim 8, wherein the rear unit, in order to receive output signals fromthe front units A₁ to A₄ of the front units A₁ to A_(M), comprises: twothird gate circuits G₃₁ and G₃₂ configured to each exclusively receivetwo signals of the output signals from the front units A₁ to A₄, andeach output a signal indicating a logical NAND between the receivedsignals; and a fourth gate circuit G₄ configured to receive the signalsoutput from the two third gate circuits G₃₁ and G₃₂, and output a signalindicating a logical NOR between the received signals.
 17. The signalmultiplexer according to claim 8, wherein the rear unit, in order toreceive output signals from the front units A₁ to A₄ of the front unitsA₁ to A_(M), comprises: two third gate circuits G₃₁ and G₃₂ configuredto each exclusively receive two signals of the output signals from thefront units A₁ to A₄, and each output a signal indicating a logical NANDbetween the received signals; and a fourth gate circuit G₄ configured toreceive the signals output from the two third gate circuits G₃₁ and G₃₂,and output a signal indicating a logical OR between the receivedsignals.
 18. The signal multiplexer according to claim 8, wherein therear unit, in order to receive output signals from the front units A₁ toA₈ of the front units A₁ to A_(M), comprises: four third gate circuitsG₃₁ to G₃₄ configured to each exclusively receive two signals of theoutput signals from the front units A₁ to A₈, and each output a signalindicating a logical NAND between the received signals; two fourth gatecircuits G₄₁ and G₄₂ configured to each exclusively receive two signalsof the signals output from the third gate circuits G₃₁ to G₃₄, and eachoutput a signal indicating a logical NOR between the received signals;and a fifth gate circuit G₅ configured to receive the signals outputfrom the fourth gate circuits G₄₁ and G₄₂, and output a signalindicating a logical NAND between the received signals.